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Abstract
The scope of the presented Thesis is mainly: Survey on the
VLSI Microlithography process flow, and reporting the faced
challenges in the sub-100nm technologies manufacturing.
Analysis and implementation of several types of Resolution
Enhancement Techniques (RET), which are essential for
different technology nodes (90nm, 65nm and 45nm)
fabrication. Elaborate on the importance of post-RET
verification approaches, and its role in the on-Silicon circuits
performance prediction. The Thesis is composed of 5 chapters:
Chapter 1: Introduction to sub-wavelength VLSI
Microlithography through related lithography simulation
environment and future approaches of Microlithography.
Chapter 2: Basic concepts of RET various solutions and
its impact on Microlithography printing yield.
Chapter 3: Post-RET verification approaches and its role
in circuit performance prediction.
Chapter 4: Relation between Lithography and Circuits
Layout design.
Chapter 5: Conclusion on the effectiveness of
implementing RET on Microlithography.