الفهرس 
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Abstract
System-on-Chip (SoC) verification is a challenging task due to the increasing complexity and diversity of SoC designs. Traditional verification methods often suffer from scal- ability issues, low reusability of testbenches, and insufficient coverage of system-level scenarios. In this thesis, we explore the existing verification challenges in SoC design and propose a verification architecture specifically aimed at addressing these challenges. The proposed verification approach and architecture aim to mitigate some of the cur- rent issues and facilitate testbench development by significantly reducing verification time and improving the reusability of testbenches.
The verification architecture in this thesis consists of two flows: block-level and system- level verification flow. Block-level verification flow checks the functionality of the blocks inside the SoC by stress testing them and trying to stimulate all possible testing scenar- ios. The verification environments built for the blocks have to be modular and reusable. Reusing the block level test cases and verification environments in the system-level en- vironment reduces the verification time and cost significantly. On the other hand, the system-level verification flow ensures proper integration and communication between the blocks while evaluating system-level scenarios. Unlike the block-level verification flow, the system-level verification does not require stress testing as it is performed at the block level.
To demonstrate the effectiveness of the proposed verification architecture, we conducted a case study on an SoC design based on the Cortex-M3 processor. Our verification process started with block-level verification, wherein we proposed reusable UVM verifi- cation environments for two common blocks in different SoCs: the processor and the bus matrix. We provided a detailed explanation of the components inside each environment, as well as the connections and flows between them. To further optimize the block-level verification process, we adopted a novel reference model approach for the Cortex-M3 pro- cessor, where we leveraged the processor simulator from Arm (Keil µVision) to act as the reference model and deliver expected results, rather than building one from scratch.
Finally, the simulation flow and results are presented, where we described how we planned, generated and executed the test cases for each verification environment. Code and functional coverage results for the Cortex-M3 processor and bus matrix are included as well.