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Abstract
In this thesis, design techniques are proposed for Analog to Digital converters, which are the core of the analog front end of wireless transceivers. Current wireless communications standards dictate a low-power high-speed circuit design. Two switched-capacitor techniques are proposed to achieve high precision despite the finite gain of operational amplifiers (opamps). Predict and Level Shift technique is proposed to enhance the effective gain of opamps through predicting the output during the sampling phase of the Analog to Digital Converter without incurring extra clock phases. charge-compensated Correlated Level shifting technique is proposed to improve the effective gain through using single-stage opamps for high-speed and resolution. An 11-bit 200MS/s pipelined ADC is designed through utilizing CC-CLS in the first stages. The ADC consumes 26 mW achieving a Figure of Merit of 73 fJ/conversion step in 130nm CMOS technology