الفهرس | Only 14 pages are availabe for public view |
Abstract CNNs are the state-of-the-art systems for image classification due to their high accuracy but their computational complexity is very high. Therefore one of the challenges in this field nowadays is the hardware acceleration for real time applications. FPGAs are the target for HW implementation as they have low power consumption and flexible architecture which fits larger CNNs despite the GPUs which consumes large power. This work discusses this problem and provides a solution that compromises between the speed of the CNN and the limited resources of FPGA. This solution depends on using parallelism and pipelining techniques inside some layers for implementing CNN using Xilinx SDSoC tool. The implementation of the design using high level language enhances the design time. In addition, it fits for larger designs compared to using only an FPGA. An Alex-Net CNN and GoogLeNet CNN are implemented successfully on Xilinx SDSoC platform and achieved a very good results. |