الفهرس 
IntroductionOnly 14 pages are availabe for public view
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Abstract
In this work, a noise-shaping successive-approximation register analog-to-digital converter (NS SAR ADC) is integrated with an inverter-based loop filter and presented thoroughly. This NS SAR ADC is robust against all process, voltage, and temperature (PVT) variations. It is also low power and serves best for low-power applications. It has an ease of technology scalability, as well. An analysis of the system design is explained along with the schematic designs of the building blocks. The simulation results are obtained and presented performing an overall performance of 12.1-bit ENOB with an 8-bit DAC array, OSR of 4, and SNDR of 70.03 dB consuming 0.64 mW and implemented on 28nm CMOS technology.
The thesis is divided into five chapters as listed below:
• Chapter 1: Introduction
In this chapter, a quick introduction to the ADC and its modern applications is given. This chapter also explains what FOM is and introduces the different types of ADC including the SAR ADC, Σ∆ ADC and fianlly, the NS SAR ADC. At the end of this chapter, the organization of this document is briefly discussed.
• Chapter 2: State Of The Art Realizations
This chapter discusses the state of the art for NS-SAR ADC. It has a defined com¬parison between this work and recent related publications. It shows the benefits and drawbacks of this work compared to the recent publications. It also illustrates the achievements of each paper and compares them and the specifications.
• Chapter 3: System-level design
This chapter defines the system-level design for the proposed NS-SAR ADC. It includes all the equations used in this thesis and their derivations along with the measurements and simulation results to illustrate the whole process of having the desired output of the NS SAR ADC.
• Chapter 4: Design of an inverter-based NS SAR ADC in 28nm CMOS technology This chapter focuses on the analysis and design phase which includes the test bench setup and the required values and variables that are used in this thesis. It has a sufficient analysis to the design of the inverter-based NS SAR ADC in 28nm CMOS technology.
• Chapter 5: Conclusion
Finally, this chapter summarizes the thesis and highlightes the main contributions. It also has some suggestions for future work for this thesis.