الفهرس 
The Thread Mapping Framework
Prediction of Throughput and PowerOnly 14 pages are availabe for public view
 |  | from | 97 |  |  |
| | | from | 97 | | |
Abstract
This thesis presents an efficient heuristic for dynamically assigning threads to system cores such that performance requirements are met while minimizing the energy con- sumed. The heuristic can be applied to heterogeneous systems and homogeneous systems with DVFS capabilities.
Summary
The thesis is divided into seven chapters as listed below:
Chapter 1 is an introduction to this research. This chapter provides an overview about the problem of thread assignment under performance constraints, the hardware systems considered in the scope of this research and the potential applications of our proposed method.
Chapter 2 provides the necessary background and explores recently-proposed related research work. Three main approaches for dealing with systems with power or per- formance constraints are discussed. Some studies propose algorithms to address the thread scheduling problem on heterogeneous multi-core systems. Others address power constraints using DVFS. Finally, several research studies propose reconfigurable archi- tectures to deal with program variations and constraints. We discuss recent proposals for these three approaches and highlight the use cases for each one as well as the systems most suitable for utilizing these methods.
Chapter 3 describes the proposed thread mapping framework. The formulation of the thread mapping problem, the system model used in this work and the proposed heuristic solution are shown. Furthermore, this chapter describes the means of applying our solution to systems with heterogeneous cores and systems with homogeneous cores with DVFS capabilities. Applying the proposed solution to two different schemes of DVFS algorithms for homogeneous chips and the benefits of each is also detailed in this chapter.
Chapter 4 shows the implementation details of the proposed framework. The prediction method utilized for estimation of power and performance values is presented, together with the associated prediction error percentage. Moreover, the data structures used in the implementation of the algorithm, to ensure that it can be brought online for hundred-core systems with minimal overhead, are described.
Chapter 5 shows the experimental setup used to conduct simulations and tests. The dif- ferent systems used for testing are described, along with their various configurations. A
x
background about the architectural simulator used for testing and the reason for choos- ing this specific tool is provided. Additionally, the benchmarks used in the simulations and their input sets are described.
Chapter 6 presents the experimental results from the simulations and an evaluation of the proposed framework. Comparisons are conducted between the results obtained for the different systems we tested our framework on as well as comparison with a recently- proposed thread scheduling heuristic. The scalability and complexity of the proposed algorithm are also evaluated.
Chapter 7 concludes this thesis. The most significant results of this work are summarized and directions for future work are provided.