![]() | Only 14 pages are availabe for public view |
Abstract The continuous effort to improve the performance of analog-to-digital converters (ADC) bas led the development of several precision techniques for ADCs. The primary objective of those precision techniques is to allevi- ate the accuracy constraints such as capacitor mismatch, charge injection, finite op amp DC gain and comparator offset. In the early years, the error correcting techniques like the ratio independent, reference refreshing, capacitor error-averaging, on-chip capacitor trimming and analog calibration were applied in the analog domain. The main drawback of these analog precision techniques is the complexity of circuit implementation. The digitally controlled self calibration and digital-domain calibration techniques were introduced to eliminate the disadvantage of the analog precision techniques but developed for successive approximation and flash type ADCs, respectively. Reduced feature size combined with lower power supply voltage are the key technology drivers resulting in reduced cost, higher speed and lower power consumption of digitally calibrated ADCs. This thesis presents a 1.0-V 13-bit 20S-MSample/s time-interleaved pipelined analog-to-digital converter (ADC) with a 9S-dB spurious free dynamicrange (SFDR), 7S.S-dB signal-to-noise-plus-distortion ratio (SNDR) over the full Nyquist band and a total power consumption of 71mW. This performance is enabled by digital background calibration of both capacitor mismatch in the multi-bit DAC and finite inter-stage gain errors. Msequence characteristics was used for the generation of the multiple orthogonal codes needed in the calibration engine. Also, a simple design for the dithered re-quantizer which precedes calibration is adopted. Digital calibration achieves an improvement of better than 23-dB in SFDR and I3-dB in SNDR. |