الفهرس 
Full System-Level Model
Simulation & Synthesis Results and FPGA PrototypingOnly 14 pages are availabe for public view
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Abstract
Chapter One : This chapter gives the motivation, objectives and outline of the thesis.
Chapter Two: In this chapter, theoretical background about high speed serial links and their importance is presented. The issues that face high speed data transmission over serial links and different techniques used to mitigate these issues are discussed.
Chapter Three : In this chapter, the system-level design of the digital equalizer is presented.
Chapter Four: In this chapter, the RTL implementation of the multi-standard Gbps all-digital serial link equalizer is presented.
Chapter Five: This chapter contains the simulation and synthesis results for the design as well as FPGA prototyping results.
Chapter Six: This chapter contains the thesis conclusion and the possible future work.