الفهرس 
Chapter 1 : IntroductionOnly 14 pages are availabe for public view
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Abstract
Asynchronous router is proposed as a robust design to mitigate the impact of process variation in Network on Chip (NoC). Network on chip interconnects and clock distribution network are considered under process variation with the advance in technology. The variation in logic and interconnect are included to evaluate the delay, throughput and leakage power variation with different NoC topologies. For asynchronous NoC design, the throughput negligibly decreases under high process variation conditions in different NoC topologies.
The effect of process variation on delay is a major reason to deteriorate the performance in advanced technologies. The performance of different routing algorithms is determined with/without process variation for various traffic patterns. A novel Process variation Delay and Congestion aware Routing algorithm is proposed for asynchronous NoC design. The novel routing algorithm outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.