الفهرس 
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Abstract
This thesis presents a very low power two-point modulated PLL-based transmitter. Detailed
system analysis is done evaluating quantitatively the effect of the VCO gain variation on the total
error vector magnitude (EVM) of the transmitter. A novel open loop self-calibrated algorithm is
proposed to overcome the VCO gain variation and to keep the total EVM level below 15% within
50μsec. This calibration can be done once after each channel switching making use of the benefit
of the small settling time of the PLL. Otherwise, the fabricated parts may be calibrated before
usage for all system channels, saving the outputs of the calibration algorithm to a look-up table
to be used during normal operation.
The thesis is divided into six chapters. Chapter 1 includes the motivation behind this work
and the thesis outline. In Chapter 2, different transmitter architectures are compared, giving
more focus on PLL-based transmitters. It also includes a literature survey on the latest research
work of ZigBee transmitters and general two-point modulated PLL transmitters; not specifically
for IEEE 802.15.4 standard.
In Chapter 3, introduction to the IEEE 802.15.4 standard is given, clarifying the 2.4GHz
band PHY specifications. A detailed system analysis is performed and system design is done to
reflect the global system results on the local block specifications. The analysis of the VCO gain
variation on the transmitter EVM level is also presented.
In Chapter 4, the transistor-level implementation of the system building blocks is presented.
This work includes the design of a 5GHz VCO followed by a current-mode logic (CML) I/Q
divider. The differential output of the divider is converted to CMOS level using differential-to-
CMOS block which drives the feedback pulse swallow divider. Also it includes the design of the
bias cell, the phase-frequency detector (PFD), the charge pump (CHP), and the loop filter.
Chapter 5 deals with the issue of VCO gain calibration. A literature survey of different methods
is presented. A novel gain calibration algorithm is proposed. Its functionality is illustrated
and system simulation results are shown. Finally, the design of different required circuits is also
illustrated.
Finally, Chapter 6 presents the total power consumption achieved. It also shows the area
estimate of each block and the total chip silicon area. A comparison between the achieved results
and other state-of-the-art research work is held. Finally, it shows the simulation results of the
PLL based on all schematics of all blocks.