الفهرس 
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Abstract
This thesis presents low-voltage, low-power, low-noise system and circuit design techniques of bio-medical front-ends. The target application is a compact and digitally-programmable neural front-end to be used in brain machine interface (BMI) systems with large number of channels in deep sub-micron CMOS technologies.
On the system level, a new mixed-signal architecture is proposed to minimize area of the neural front-end to be used with the emerging multi-channel BMI systems. The conventional electrode offset suppression technique is analog high-pass filtering using large input coupling capacitors, which consume large area, and pseudo-resistors, which varies significantly with process, voltage, and temperature (PVT) variations. The proposed front-end employs a single multi-bit ΣΔ digital-to- analog converter (DAC) with dynamic element matching (DEM) and a flexible digital filter in the feedback to suppress electrode DC offset up to ±50 mV and digitally control the front-end closed loop transfer function. The flexible digital filters can be configured to acquire different neural signal: Local field potential (LFP) signals only, spikes signals only, or both.
On the circuit level, different analog and digital blocks in the neural front-end exploit low supply voltage of 0.8 V to minimize the power consumption and to make the neural front-end more compatible with emerging wireless powering schemes. This low supply voltage imposes limitation in the dynamic range. Thus, all analog blocks utilize fully differential circuit implementation.
Furthermore, the usage of the mixed-signal feedback relaxes the requirements of the dynamic range as it desensitizes the overall gain of the neural front-end. Hence, an open-loop compact low-noise neural amplifier is used as the first block in the front-end. A second order Gm-C antialiasing filter is used to filter out ΣΔ DAC quantization noise. A 8-bit 800 kS/s SAR ADC is proposed with 48.5 SNDR and 11.3 fJ/conversion-step to be multiplexed by 4 channels.
A top down design methodology was adopted to implement the proposed mixed-signal front-end in a standard 0.13 μm CMOS technology. A complete frequency domain linear model is developed where the system performance is analyzed and optimized then specifications of different blocks are calculated. Moreover, a complete time-domain behavioral model is built using Matlab/Simulink to account for non-linearities and non-idealities of different blocks in the system. The whole neural front-end achieves a low input-referred noise of 4.83 μVrms for a signal bandwidth of 10 kHz using a compact and highly programmable architecture. It consumes 8.8 μW from 0.8 V supply while occupying 0.046 mm2.