الفهرس 
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Abstract
Over the last few years, great advances have been made in mobile
communication technology. The third generation (3G) mobile systems provide
further improved network capacity, high speed packet data and voice and real-time
multimedia services. WCDMA has become the major 3G air interface in the world.
Modern wireless communication systems utilize certain digital signaling techniques
known as channel coding to improve performance, efficiency and to achieve reliable
communication over noisy and fading channels.
WCDMA employs convolutional coding to encode voice and MPEG4
applications at maximum data rate 2 Mbps. Viterbi algorithm is the powerful
method for decoding convolutional codes. Several hardware architectures are used
to implement Viterbi decoder. Serial or parallel schemes are used to implement
ACS computation block. Also two main hardware architectures are used to
implement Survivor memory unit of Viterbi decoder, Trace back (TB) method and
Register Exchange (RE) method. The complexity of Viterbi decoding is an
exponential function of the constraint length. WCDMA requires decoder with
constraint length of 9 (256 states), which poses an implementation challenge.
In this thesis, Matlab simulation Model as well as hardware architecture of
WCDMA Viterbi decoder was designed with specifications according to 3GPP
standard, where the code rates are 1/2 and 1/3. The proposed decoder uses serial
architecture combined with modified version of register exchange method for
achieving small area. The hardware prototype is successfully implemented on
Xilinx Virtex-5 family. The core occupies about 5% of total FPGA slices & 1% of
block RAM resources. Furthermore, the achievable core throughput is 5 Mbps,
which exceeds target speed. Also BER performance shows that at Eb/N0 =10-3, the
coding gain of approximately 4.8 dB is achieved for code rate = 1/2 and 5.1 dB for
code rate = 1/3