الفهرس 
IntroductionOnly 14 pages are availabe for public view
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Abstract
IGBTs have proven through the last two decades that they are the suitable switch up to the medium range of power applications; mainly due to their low conduction losses. However, as the switching losses become the significant component of losses when frequencies going higher, as IGBTs suffer from higher overall losses and longer switching times when compared to MOSFETs. The need for MOSFET at these high frequencies becomes inevitable.
However, MOSFETs should have minimal resistance when the device is conducting and should sustain high voltages when the device is OFF to still be effective in such applications. Unfortunately, a higher breakdown voltage yields to further increase in the ON state resistance according to what is called rule of ”silicon limit” (i.e., RDSon a V;;s, where Vbr is the breakdown voltage). This rule means that increasing breakdown voltage can result in a significant increase in ON resistance causing higher conduction losses. Furthermore, for the same current rating, the switching speed of a MOSFET with higher breakdown voltage rating is usually slower which means higher switching losses. As a result, the decreasing of the ON resistance in the high-voltage power MOSFETs is the very important challenge for the producers of these devices.
In the late 1990’s the super junction MOSFET transistor was launched. It combines the low on state losses of an IGBT and the low switching losses of a MOSFET. In this study, CoolMOS transistor from Infineon Technologies has been used which is based on the super junction topology.
CoolMOS has shown great parameters over traditional MOSFET. Regarding area specific ON-resistance, a 600 V CoolMOS offers a shrink factor of 5 versus the actual state of the art in power MOSFETs keeping the blocking voltage of the transistor unaltered. It reduces Miller capacitance and input capacitance by a factor of two versus the state of the art which leads to a very small gate charge and, hence, very fast switching and very small switching losses. Also, the active chip size shrinks by factor of 4 in comparison to a conventional MOSFET. CoolMOS keeps enhanced Safe Operating Area which make the device sustain current which exceeds the rated nominal current by a factor of 5 for a period of lOJlS which is sufficient for an over current detection.
However, CoolMOS suffers from two main problems. The first one is the device parameters high sensitivity -especially breakdown voltage- to doping concentration. This makes its manufacturing process very critical and hard due to difficulties in formation of perfect charge-balanced SJ p-n columns by the current process technology, especially for devices with small widths and voltage ratings below 180 V. But, actually, this problem is not the scope of this study and it will be mentioned briefly in chapter 2.
In bridge circuit topologies, provisions must be made for reverse current flow across the device. Just as in conventional power MOSFETs, the parasitic P-j-N diode in the CoolMOS can be utilized to replace the external anti-parallel diode. However, successful implementation of this concept demands that the characteristics of the integral diode exhibit low on-state losses, minimal stored charge i.e. small peak reverse recovery current and a soft reverse recovery characteristic. Unfortunately, the CoolMOS diode is found to be snappier than that of a normal power MOSFET which make it difficult to use switched inverters and that is the second problem of CoolMOS.
Many mitigation techniques were proposed for CoolMOS body diode characteristics but they impose either change in manufacturing process such as ir, CoolMOS devices by electrons, inserting a moderately doped N-buffer incorporation of the Schottky contact in the CoolMOS structure or addil components to the system such as blocking diodes which will be. costly and will voltage DROP, size and losses.
In this study, a novel technique is proposed to mitigate snappy characteristics of C body diode; which employs CoolMOS in a Current Source Inverter topology as with Silicon Carbide Schottky Diode. This technique shows great improvement switching current peak and switching losses. PSpice simulation program is use preliminary results. Firstly, it is used to study effect of different parameters (DC’ Load Current, ... ) on the peak of the reverse recovery current, then it is l comparison of this peak value when employing single phase VSI & CS! tOI comprising resistive and inductive loads.
As losses value couldn’t be approved from simulation due to various approxima devices models; an experimental setup has been built to boost the validity of p: techniques. Three phase VSI & CSI inverters are built; values of switching lm obtained for both resistive & inductive loads which revealed the great impro achieved using the proposed topology.