الفهرس 
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Abstract
Data Security is the most important issue nowadays. A lot of cryptosystems are introduced to provide security. Public key cryptosystems are the most common cryptosystems used for securing data communication. The common drawback of applying such cryptosystems is the heavy computations which degrade performance of a system. Modular multiplication is the basic operation of the common public key cryptosystems such as RSA, Diffie-Hellman key agreement (DH), EIGamal and Eec. A lot of researches are now directed to reduce the overall time consumed by modular multiplication operation.
In this thesis, we propose two efficient interleaved modular multiplication algorithms and their corresponding architectures. The first algorithm is called Radix-4 Modified Interleaved Modular Multiplication based on Sign Detection (Radix-4 MIMM). Radix-4 MIMM is adaptation of Modified Interleaved Modular Multiplication based on Sign Detection (MIMM). MIMM computes modular multiplication without a pre-computational phase, or predefined sets for moduli. A pre-computational phase requires significant time for computations and predefined sets for moduli restrict cryptosystems. Radix-4 MIMM enhances the performance of MIMM by scanning two bits per iteration instead of one bit. The relative speed up gain of Radix-4 MIMM architecture compared with MIMM architecture is up to 40%.
The second proposed algorithm is called Efficient Interleaved Modular Multiplication based on Sign Detection (EIMM). EIMM is a parallelized version of the standard interleaved modular multiplication algorithm. EIMM computes all possible intermediate results in parallel and confirms the correct intermediate result using sign detection technique. EIMM computes modular multiplication without a pre-computational phase, or predefined sets for moduli. The relative speed up gain of EIMM architecture compared with MIMM architecture is up to 101%.
Hardware algorithms have been performed Xilinx FPGA.
implementations of the existing and the proposed been performed. Simulation, synthesis and analysis have for bit lengths 32, 64, 128, 256, 512 and 1024 bits on