الفهرس 
CHAPTER 1: INTRODUCTIONOnly 14 pages are availabe for public view
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Abstract
This thesis suggests a new design of electronic circuit that based on neuron MOS technology to be used in associative processor system. This design can operate as a memory cell for storing data and as a matching cell for comparison among the input signals with small die area, low consumption power, high output linearity, small total harmonic distortion and high efficiency for weight-update process. The thesis introduces a survey on artificial neural network and arithmetic operations that organize its work. It includes the most recognizable characteristics of the artificial neural network. Several designs of multiplier circuits were discussed and studied to choose the best for building up this technology. Then, a new CMOS four-quadrant differential multiplier circuit featuring with small area and low power consumption is suggested and studied. The research studies a multiplier circuit known as exponential pulse decay modulation (EPDM) multiplier. The study handles circuit simulation by SPICE program and demonstration of its advantages and disadvantages. Besides, an alternative exponential pulse decay modulation multiplier scheme with double MOS differential configuration resistor is suggested and studied. This multiplier enhances the output linearity and removes the influences of second order effects of MOS transistors on circuit operation. These properties make this new multiplier suitable enough for implementation of a new memory-matching cell. The new matching memory cell has been studieded and simulated by SPICE program. The thesis suggests subject for future research in this field.