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Abstract
The Advanced Encryption Standard (AES) is the new standard for cryptography and has gained wide support as means to secure digital data. In this thesis, we explored design and implementation approaches of the AES on field programmable gate arrays (FPGAs). We introduced the heuristic design techniques of the AES substitution boxes and we suggested an AES substitution box with good cryptographic properties. Tradeoffs of speed vs. area that are inherent in the design of a security processor are explored. Two implementations of the AES on Xilinx Virtex 4 FPGA are introduced, the first design is called optimized area AES which is based on the basic architecture of the AES, the second one is called optimized speed AES which is based on the sub-pipelined architecture of the AES. An AES crypto processor with serial interface was implemented and it could be used with any of our designed encryptor or decryptor. Two applications of the AES algorithm in feedback mode of operation were implemented on Xilinx Virtex 4 FPGA, one of the applications is the AES key wrap algorithm which could be used in the key transfer in unsecured communication channel, and the other application is the AES block cipher based deterministic random bit generator (DRBG) which could be used as a pseudo random number generator (pRNG). Loop unrolled architecture is used in the implementation of the AES in feedback mode of operation. A complete simulations and implementation results are provided for all of our designs.